Submicron manufacturing uses lithographic techniques to build up layers of materials on a substrate to create transistors, diodes, light-emitting diodes (LEDS), capacitors, resistors, inductors, sensors, wires, optical wires, microelectromechanical systems (MEMS) and other elements which collectively produce a device that serves some function. Substrate lithography is a printing process in which a mask, sometimes called a reticle, is used to transfer patterns to a substrate to create the device. In the production or manufacturing of a device, such as an integrated circuit or a flat panel display, substrate lithography may be used to fabricate the device. When the device to be created is an integrated circuit, typically the substrate is a silicon wafer. In creating an integrated circuit, the lithography is semiconductor lithography which for high volume production is typically a substrate lithography. Other substrates could include flat panel displays, liquid panel display, a mask for flat panel display, nanoimprint masters, or other substrates, even other masks.
In semiconductor lithography, the mask or multiple masks may contain a circuit pattern corresponding to an individual layer, or a part of a layer in multiple patterning processes, of the integrated circuit. This pattern can be imaged onto a certain area on the substrate that has been coated with a layer of radiation-sensitive material known as photoresist or resist. Once the patterned layer is transferred the layer may undergo various other processes such as etching, ion-implantation (doping), metallization, oxidation, and polishing. These processes are employed to finish an individual layer in the substrate. If several layers are required, then the whole process or variations thereof will be repeated for each new layer. Eventually, a combination of multiples of devices, which may be integrated circuits, will be present on the substrate. These devices may then be separated from one another by dicing or sawing and then may be mounted into individual packages.
Optical lithography may be 193 nm light, with or without immersion, or extreme ultraviolet (EUV) or X-ray lithography, or any other frequencies of light or any combination thereof.
Optical lithography that uses 193 nm light waves works with refractive optics and transmissive photomasks or reticles. The masks block, partially block, or transmit the light waves selectively on to a substrate, which is typically resist-coated during the lithographic process, to partially expose or to expose different parts of the substrate or some material on the substrate. The masks are typically at 4× magnification of the target substrate dimensions.
Extreme Ultraviolet Lithography (EUV) uses approximately 13.5 nm wavelength of light with reflective optics. Some implementations use an anamorphic mask with magnifications of 8× in one dimension and 4× in the other dimension.
In general, smaller wavelengths of light are able to resolve finer geometries, finer spaces in between geometries, and a higher frequency (density) of features on the substrate. Also in general, smaller wavelengths of light are more difficult to reliably produce and control. Economically, it is best to use the largest wavelength of light that is able to resolve the feature sizes, spaces, and frequencies that are needed for the device. It is therefore of interest to enhance the resolution achievable on the substrate with any given wavelength(s) of light.
For any lithography of a particular resolution, additional techniques such as off-axis illumination, phase shift masks, and multiple patterning extend the resolution capabilities. When multiple patterning is used, a single substrate layer is exposed multiple times, each time using a different mask which is called a mask layer.
Masks are created by electron beam (eBeam) machines, which shoot electrons at a photo resist coating a surface, which is then processed to produce the desired openings in the mask. The amount of energy delivered to a spot on the mask is called the dose, which may have no energy at a dose set to 0.0 and a nominal dose set to 1.0 by convention. A pattern will be registered when the dose exceeds a certain threshold, which is often near 0.5 by convention. Critical dimension (CD) variation is, among other things, inversely related to the slope of the dosage curve at the resist threshold, which is called edge slope or dose margin.
There are a number of technologies used by eBeam machines. Three common types of charged particle beam lithography are variable shaped beam (VSB), character projection (CP), and multi-beam projection (MBP). The most commonly-used system for leading edge mask production is VSB. VSB and CP are sub-categories of shaped beam charged particle beam lithography, in which an electron beam is shaped by a series of apertures and steered to expose a resist-coated surface. MBP uses plurality of charged particle beams whereas VSB and CP machines typically have a single beam.
It is difficult to print features whose size is similar to or smaller than the wavelength of the light used for lithography. The industry has applied various techniques to address the difficulty of reliably printing a desired shape on the substrate. A computational lithography field has emerged to use computing to enhance the substrate lithography, which in semiconductor lithography is also referred to as wafer lithography. Reticle Enhancement Technologies (RET) include computational methods and systems to design the target reticle shapes with which to project the desired pattern on the substrate more precisely and more reliably across manufacturing variation. RET often use computation to enhance an image on a mask, to print a desired substrate pattern more accurately and more reliably with resilience to manufacturing variation. The two common techniques in RET are Optical Proximity Correction (OPC) and Inverse Lithography Technology (ILT). OPC and ILT are often iterative optimization algorithms that adjust parameters defining the mask until the predicted pattern on wafer is within acceptable tolerances for a set or a range of conditions. OPC manipulates mask geometries and simulates the wafer pattern near target edges. ILT manipulates the mask transmission as pixels, and ILT typically simulates the entire wafer pattern, a process known as dense simulation. An iterative optimization algorithm typically consists of: (1) evaluate a proposed solution to assign a cost which is trying to be minimized; (2) if cost is below a cost criteria, stop; (3) calculate a gradient for each element of the proposed solution which would lead to a lower cost; (4) adjust the proposed solution according to the calculated gradients; (5) go back to (1). Costs are typically defined with positive values where zero is the best possible score as assumed here. However, alternative cost definitions may be used.
RET in general means to improve the printability of all desired features at nominal (expected) manufacturing conditions and within expected manufacturing variation around the nominal manufacturing conditions. Since manufacturing processes are not perfect, the design needs to be resilient to certain expected manufacturing variation. A larger process window means more resiliency to manufacturing variation, specifically that pattern discrepancies through defocus and dose variation are within an acceptable tolerance. Providing sufficient process window for as many of the features as possible is a goal of RET. The percentage of chips that function as specified after fabrication is often referred to as the yield. Many factors affect yield. Improving the process window is generally considered among those skilled in the art to correlate to improving yield.